Sigasi Magic HDL

A local MCP server that lets an AI assistant analyze and verify Verilog, SystemVerilog and VHDL hardware-design projects.

What you can do

Analyze Verilog, SystemVerilog and VHDL projects from an AI agent over MCP, so the assistant can inspect hardware-design code in place rather than guessing from pasted snippets. Verification of those projects is the stated purpose; the manifest lists no individual tools, so the exact operations are not documented here. It runs as a local process on the user's own machine, working against the project files there.

When to use it

Worth adding when an assistant is helping with FPGA or ASIC design work in Verilog, SystemVerilog or VHDL and needs to analyze or verify the actual project rather than reason about code in isolation. It is a desktop-only tool, so it suits local development machines.

Requirements

Runs locally over stdio, launched with npx from the npm package @sigasi/magic-hdl, so Node.js and network access for the package are needed. A Magic HDL license key is supplied through the MAGIC_HDL_LICENSE_KEY environment variable, but only when the machine has no stored key yet; the documented setup path is the magic-hdl login and magic-hdl setup commands.