Multisim MCP

Connect to the local Multisim Automation API.

无需输入参数。

Check local EDA runtime compatibility without starting Multisim.

Register an existing complete experiment directory as MCP Resources. Use this after a server restart when the experiment was generated earlier. Only the fixed high-level experiment artifact set is exposed.

List artifact metadata, hashes, MIME types, and safe access capabilities.

Read one bounded page from an allowlisted text experiment artifact.

Export an artifact beneath MULTISIM_MCP_ARTIFACT_EXPORT_DIR.

Return a compact report, verification, and artifact summary for agents.

Audit SPICE dialect, model hashes/licenses, and static backend risks.

Numerically compare common signals from two registered EDA experiments.

Register a completed sweep directory and return opaque MCP Resources.

Compute explicit metrics from a registered experiment's raw data.

Read DC, true RMS, AC RMS and range from experiment data.

Use the Bode Plotter adapter on an AC-sweep experiment.

Use the Logic Analyzer adapter to digitize traces and list edges.

Export bilingual HTML/PDF reports and a reproducibility manifest.

List portable built-in and local declarative component adapters.

无需输入参数。

Convert supported native DFF carriers into an explicit ngspice reference. The returned netlist is not run automatically and never replaces the source design. It maps native ``D, ~PR, ~CLR, CLK, Q, ~Q, GND, VCC`` pins to the portable ``@DFF`` adapter, inserts explicit control inverters for active-low ``~PR/~CLR``, and records the behavioral-only claim. Pass the returned ``netlist`` explicitly to ``run_spice_netlist`` with ``backend='ngspice'`` when a reference run is desired.

Build and run an explicit ngspice behavioral reference in one call. This workflow is intentionally opt-in: it only accepts a netlist containing a supported native ``DFF8``/``7474N``-family carrier, converts that carrier to the portable ``@DFF`` reference, and then runs the converted netlist through the explicitly selected ngspice backend. The source design is not modified, and the result must not be interpreted as native Multisim 74LS74 timing or electrical-equivalence evidence.

Evaluate explicit design requirements; unsupported evidence stays unverified.

Validate and preview parameter, tolerance, temperature, or Monte Carlo runs.

Return comparable technical方案 without generating or executing a circuit. The result is a bounded planning-only ``DesignPlan``. It contains a deterministic recommendation, alternative implementation paths, trade-offs, and explicit assumptions. Netlists, schematics, files, and simulations are intentionally deferred until a caller selects an option in a later step.

Review an optimisation contract before running a baseline experiment. The tool normalises measurement requirements, separates hard constraints from soft objectives and preferences, and detects obvious contradictory bounds for the same signal. It never creates a circuit, writes files, or starts a simulation; a clean result only means the declared contract is internally coherent.

Bind reviewed requirements to an existing design snapshot without edits. Voltage and current signals are matched against design nets and component references. Unrecognised signal text is reported for explicit aliasing; no .ms14 file, source netlist, or simulation state is modified.

Lock one planning option without generating or executing a circuit. The input plan digest is checked before selection. The returned envelope binds the source and selected digests so a later generator can require an explicit, untampered handoff.

Prepare a reviewable electrical specification from a selected plan. This read-only step lists required electrical parameters, planned modules, analyses, and validation gates. It requires a valid selection digest and never creates a CircuitDesign, netlist, schematic, file, or simulation.

Prepare a logical netlist draft after explicit specification approval. The result contains block-level nets, connections, unresolved component requirements, and derived constraints. It is not executable SPICE and never creates a CircuitDesign, schematic, file, or simulation.

Resolve logical roles into reviewable component candidates and rating gates. This remains a read-only planning step. It does not choose a silent part number, create a CircuitDesign, generate SPICE, write a file, or start a simulation. A later stage must provide model provenance and explicit human approval before compiling an executable netlist.

Record explicit human approval for a complete component resolution. This is still a review artifact. It does not generate SPICE, create a CircuitDesign, write a file, render a schematic, or start a simulation; those actions require a later compiler and separate approval gates.

Compile an approved logical draft into a bounded pin-level preview. Only options in the compiler support matrix are accepted. External model bytes, when present, are re-hashed beneath ``MULTISIM_MCP_MODEL_ROOT``. Optional experiment_fixture composes an explicit DC/AC source and source impedance before review, currently signal-active/14.3 only. It requires schema_version, target_version, dc_voltage_v, source_impedance_ohm and included_load_ohm; optional ac_amplitude_v/ac_phase_deg are small-signal AC. The resulting netlist review requires confirm_fixture and fixture_sha256. The result stays in memory and does not write files, create a schematic, start Multisim, or run a simulation.

Record explicit human approval for one immutable netlist preview. The approval binds the compiled CircuitDesign and SPICE digest. It does not write a schematic, create a project file, add stimuli, or start a simulation; those remain separate downstream gates.

Record explicit approval for one safe simulation plan. The artifact binds the approved executable-netlist preview to the exact analysis commands, measurement requirements, and theoretical values in an ``ExperimentSpec``. It does not create a schematic, write files, or start a simulation; ``run_verified_circuit_experiment`` must validate it again.

Return the bilingual five-waveform course-design contract. With no arguments this returns the safe behavioral reference model. A caller may provide a native Multisim-compatible netlist and analysis commands to keep the same explicit requirement gates while changing the implementation. This tool only builds/validates the contract; use ``run_verified_circuit_experiment`` for measured evidence.

Queue a durable, cancellable experiment in an isolated worker process. Prefer this tool for long experiments. Poll ``multisim://jobs/{job_id}`` or call ``get_experiment_job``. Completed jobs return the same experiment result and resource handles as ``run_circuit_experiment``. When approval artifacts are supplied, all three are persisted with the job and verified again inside the isolated worker before execution.

Return durable progress, failure diagnostics, or the completed result.

List recent durable jobs without returning their potentially large results.

Cancel a queued job or safely stop its isolated worker process.

Queue a fresh attempt using a failed, cancelled, or timed-out job spec.

List native component families available to the schematic generator.

Disconnect from Multisim and release the open circuit.

无需输入参数。

Open a Multisim design file and return circuit info.

Create a new empty Multisim design.

无需输入参数。

Return name, file, simulation state, and last error for the open circuit.

无需输入参数。

List component reference designators. 0 returns all.

List simulation inputs. 0 returns all.

List simulation outputs. 0 returns all.

Configure an output request before RunSimulation.

Fetch data for an output that is ready; shape depends on analysis type.

Run a transient simulation and return downsampled time/real data.

Run DC operating point analysis for the given outputs.

Run AC sweep and return frequency/real/imag rows.

Run AC analysis at a single frequency.

Inject a sampled waveform into a simulation input.

Inject a raw (time, value) waveform into a simulation input.

Clear injected data from a simulation input.

Stop the currently running simulation.

无需输入参数。

Save the circuit, optionally to a new path.

Export the circuit schematic as an image.

Export the SPICE netlist to a text file.

Export the open Multisim circuit into a validated design snapshot. The source ``.ms14`` remains untouched. The exported netlist and snapshot are written only below ``output_dir``; COM enumeration is retained as evidence alongside the parsed ``CircuitDesign``.

Run an approved, bounded COM sweep and restore every original R/L/C value.

Rank completed native sweep records against an explicit scalar objective.

Prepare a standard reversible DesignPatch from the best native sweep result.

Apply an approved native sweep patch to a new .ms14 copy and reopen the source.

Compare the best native sweep candidate against the original-value baseline.

Export a bilingual native sweep comparison report and integrity manifest.

Export the bill of materials to a text file.

Run an unrestricted Multisim command file when explicitly enabled. This advanced tool is disabled by default because command files can access the filesystem and may expose engine-specific command execution features.

Run SPICE through Multisim or ngspice with safe analysis commands. The default path rejects scripting, shell escapes, file commands, and arbitrary command sourcing. Unrestricted engine commands require both the ``unsafe_commands`` argument and an explicit server-side environment flag.

Validate a structured multi-board request and return a planning-only contract. This tool never opens Multisim, writes a project, or starts simulation. A feasible candidate may include board-local logical artifacts, but native generation and acceptance remain a separate explicit step.

Lock a structurally ready multi-board candidate without native execution.

Run or preview native acceptance for a selected structured multi-board request. The request is re-planned and a structurally ready candidate is selected before any schematic or COM work. Preview mode is side-effect free. Execution opens, saves, reopens, reads back and simulates each board in the installed Multisim version, then compares explicit fixture observations and a full-design reference. ``analysis`` accepts ``dc`` (default), ``tran`` or ``ac``. Native results retain complete sampled axes; TRAN and AC compare every aligned sample (AC compares real and imaginary parts) without interpolation by default. Set ``analysis_options.series_alignment`` to ``"linear"`` only when independently simulated boards have different adaptive axes; the bounded resampling basis is recorded in the result. Scalar endpoint values remain a report summary only.

Use a configured model to propose a requirement, then validate it locally. The model receives one narrow tool and cannot return a schematic, file path, shell command or executable SPICE. The resulting proposal is still only a plan until native execution is requested separately.

Model-propose, locally validate, then optionally run the native RC flow.

Queue an auditable model-to-Multisim engineering run. The worker persists the model plan before native execution and exposes the same durable status/SSE contract as other long-running experiment jobs.

Queue a native RC, RLC, or OPAMP engineering workflow.

Preview or execute supported natural RC requirements in a new output directory. Explicit execution generates .ms14 files, runs native OP/AC/TRAN for bounded candidates and exports acceptance evidence. No external AI model or source- netlist simulation fallback is used. Review disclosed assumptions in preview.

Translate a bounded natural-language electrical request into a validated plan. The returned netlist is a proposal only. Callers must review it, create the native schematic, and run native measurements before accepting a design. Ambiguous requirements fail closed instead of selecting an unverified topology.

Build a bounded RLC contract and SPICE preview without native execution. Native RLC acceptance remains disabled until the corresponding Multisim measurement adapter has passed a real-version regression.

Preview or execute bounded RLC candidates with native Multisim acceptance.

Build a bounded non-inverting OPAMP5 contract and SPICE preview.

Preview or execute the bounded non-inverting OPAMP5 native workflow.

Build and verify a composed linear analog design in native Multisim 14.3. The host AI translates the user's request into proposal fields: title, application, netlist, probe_nets, experiments (op/ac with commands), checks. Accepts up to 64 R/C/L, DC/AC voltage sources and ideal OPAMP5 devices in any connected topology. Also accepts explicit LM324AJ from a licensed local template pack, with native model identity verification and OP/AC/TRAN sampled checks (no independent ideal-model equivalence). Other vendor models and semiconductors are rejected. Checks contain analysis, net, quantity, min/max, optional reference_net; AC requires frequency_min_hz/max_hz. Use quantity=value for OP, magnitude or phase_deg for AC. A reference_net checks the voltage ratio. Every sample in the specified band must pass. LM324AJ requires OP and AC and checks for every analysis. Its optional transient uses quantity=value with time_min_s/time_max_s, and a DC/AC voltage source may append PULSE(low high delay rise fall width period). Preview performs no writes/COM. Execute creates a new .ms14, verifies every native pin, runs native analyses, checks ideal-model phasors against independent nodal equations, exports schematic PNG, matrices, CSV and HTML. Missing checks yields reference-only acceptance, not requirements approval. Optional executable_netlist/netlist_approval must be supplied together and bind proposal.netlist exactly to a reviewed experiment_fixture preview. This path also checks passive values and the saved ideal VCVS model. The native proposal's experiments/checks and execute flag authorize the run; this path does not claim a separate simulation-plan approval artifact.

Translate a bounded sensor analog-front-end request into a native proposal.

Generate and verify a sensor front end from Chinese/English requirements.

Translate a bounded DC divider request into a native proposal.

Generate and verify a resistive DC divider from a natural-language request.

Plan a bounded single-NPN common-emitter amplifier request.

Build a bounded 2N3904 amplifier and verify native OP/AC/pulse measurements. Requires a licensed local pack with VDC and VPULSE carriers. Saves the editable schematic, PNG, raw measurements, model/pin checks and report. Success verifies declared sampled conditions; visual review is still needed.

Plan a 4–18 Vrms, 50/60 Hz 1N4001GP bridge with a 5–200 mA resistive load.

Build a local native bridge, export its schematic/report and verify OP/transient evidence. Requires licensed AC_VOLTAGE and full 1N4001GP carriers. Checks saved values, diode models/pins, input RMS, DC mean, ripple, resistive load current and settling. Preview by default. This bounded simulation does not certify a physical power supply.

Minimize bridge capacitance by native experiments, tolerance cases and saved-file replay. Preview discloses nine discrete candidates and fixed input/load/capacitance cases. Execution may take several minutes. Keeps every failed candidate, checks startup, reopens the selected saved circuit and exports comparison reports. No physical certification.

Create an editable Multisim schematic from a supported SPICE netlist. Supports RLC components, scalar/waveform voltage and current sources, B/E/F/G/H/T primitives, modeled semiconductors and switches, OPAMP5, and user-local verified TIMER8/LM555CN and DFF8/7474N native carriers, generic two-to-sixteen-terminal X subcircuits, digital devices, ground, named nets, wiring, and deterministic layout. Compatible inline subcircuits are recursively expanded into editable primitives; unsupported macro-model constructs remain explicit carrier-only evidence. Generated schematic probes remain experimental. The high-level experiment tool obtains authoritative data from the same source netlist through Multisim's command engine. ``component_positions`` optionally maps refdes -> [x, y] sheet coordinates (example: {"R1": [36, 117]}). Listed components are placed exactly there before the wire router runs, so all wiring follows; unlisted components keep the deterministic auto-layout. When ``executable_netlist`` and ``netlist_approval`` are both supplied, the approval is revalidated against the immutable compiled preview before any schematic work begins. The supplied ``netlist`` must exactly match the approved preview's bound SPICE text. This path opens schematic generation only; it does not approve or start a simulation. When ``require_layout_pass`` is true, geometry findings are a delivery gate: the XML preflight and layout report are retained for repair, but no encoded ``.ms14`` file is produced until the layout passes.

Create a schematic, run a safe Multisim analysis, and export a report. This synchronous compatibility tool blocks until completion. For queueing, progress, cancellation, persisted state, and worker recovery, prefer ``submit_circuit_experiment``.

Run an ExperimentSpec and persist evidence-backed requirement verdicts. When the three approval inputs are supplied, the exact executable-netlist and simulation-plan handoff is revalidated before any schematic or simulation work begins. The legacy direct-spec path remains available for compatibility; it does not claim this additional approval provenance.

Diagnose a circuit without modifying it or silently guessing repairs. Structural checks require only ``design``. When ``experiment_dir`` is supplied, its artifact integrity manifest and canonical netlist are verified before requirement, convergence, BJT, or op-amp evidence is used. An optional bounded ``simulation_failure`` object may contain code, type, stage, and message fields from a failed run.

Retest one explicit reversible patch against its unchanged baseline. The service runs exactly two verified experiments under the same hard requirements, writes before/after deterministic diagnoses and an inverse patch, and never persists the candidate as the source design. A passing result remains subject to the separate local approval workflow.

Approve one exact patch apply or revert and write its bearer token locally. The one-time token is written to ``token_output`` and is intentionally omitted from the returned MCP payload. Pass exactly one of ``patch_path`` or ``revert_transaction``; this step never changes the design.

Consume a file-backed approval and durably apply one design patch.

Consume a separate approval and durably revert one patch transaction.

Recover one abandoned patch journal after its owner process has exited.

Approve a patch plus its exact verification and commit contract.

Run the approved experiment and commit only when every requirement passes.

Finalize or safely abort a crash-interrupted verified patch workflow.

Evaluate bounded component-value candidates without modifying the source design. The baseline consumes one experiment from ``spec.max_experiments``. When ``requirement_review`` is supplied, its verified hard constraints and a uniquely matched soft objective fill the spec before validation. Values may be explicit or generated from bounded E12/E24/E48/E96 ranges. Electrical, optional in-stock, and maximum variable-cost rules are hard constraints; failed/unverified candidates are never feasible, and the returned best patch still requires the separate local approval workflow before persistence.

Attach bounded single-board layout evidence to an optimization directory. The parameter optimization must already have produced its auditable directory. Every persisted candidate patch is replayed, evaluated by the deterministic layout validator, and ranked together with its electrical objective. ``materialize`` optionally emits candidate ``.ms14`` files; native Multisim save/reopen and simulation acceptance remain a separate explicit gate.

Run auditable mixed topology/value multi-objective global optimization. When ``requirement_review`` is supplied, its verified hard constraints and matched soft objectives fill the multi-objective spec before validation. Small declared domains are exhaustive; larger domains use deterministic Halton space filling. Every candidate runs a real verified experiment, failed hard constraints are excluded, and the result contains an epsilon-aware Pareto front. No candidate is persisted automatically.

Queue durable mixed topology/value Pareto optimization. Completed candidates are integrity-checked and reused after restart. An interrupted candidate is rerun in a new attempt directory. No recommended patch is persisted into the source design automatically.

Autonomously diagnose, propose, simulate, and select a repair candidate. The configured model may propose bounded parameter or topology patches, but every candidate is revalidated and simulated locally. The final all-pass candidate is returned as one reversible patch against the original design; applying it remains a separate explicit approval operation.

Queue durable model-planned correction with round-level recovery. The persisted provider configuration is validated and secret-free: it contains only endpoint/model metadata and environment-variable names. API keys are resolved by the isolated worker and are never written to job state. Completed rounds are evidence-revalidated; an incomplete planning round is replanned in a new attempt directory. No patch is applied automatically.

Queue a durable optimization with candidate-level crash recovery. Completed candidates are evidence-verified and reused after a worker or MCP restart. An interrupted candidate is rerun in a new attempt directory. The result still returns only a proposed patch and never modifies the design. Set ``resume_existing`` only to adopt a matching interrupted output folder.

Rank complete designs or approved in-memory patches using one contract. A normal item contains exactly ``variant_id`` and ``design``. A patch item contains exactly ``variant_id`` and ``patch`` and requires ``base_design``; the patch is validated and applied in memory before the same experiment service evaluates it. Patch JSON is persisted beside the candidate design for review. All requirements remain hard constraints, only finite measured passes are ranked, and no source design is modified or automatically adopted.

Run a transactional parameter, tolerance, temperature, or Monte Carlo sweep.

Queue a durable sweep in the same isolated, cancellable worker system.

Write a Markdown report for the open circuit and analysis results.

Read the current value of an R/L/C component through RLCValue.

Set an R/L/C component value through SetRLCValue.

Decode a .ms14 file to editable XML using ewd.

Encode an XML design back to .ms14 using ewe.

List the sheet position (x, y) of every component in an .ms14 file. Decodes the design with the packaged ewd codec and reads each component symbol's translation pair (Transformer-M20/M21). No Multisim session is required. With ``output_xml`` the decoded XML is also written there for offline inspection.

Move components inside an .ms14 file to new sheet coordinates. ``positions`` maps refdes -> [x, y] in sheet units (the builder's auto-layout grid step is 270 x 216; use ``list_component_positions`` to read current values). ``mode="relative"`` treats the values as deltas; ``anchor="pin_center"`` matches the builder's component_positions anchor; ``snap`` rounds onto a grid (9 pt = the builder's normalization grid). Batch-safe: any number of components moves in ONE decode/edit/encode cycle. Attached wires are re-routed with the same obstacle-aware router used at build time. Per Multisim's wiring model, wire endpoints are FIXED references (component ports / joined segments) -- rerouting only changes the drawn path, never which endpoints a wire connects. The result includes ``overlaps_after`` so you can confirm immediately whether the new arrangement still has overlapping bodies. When ``output_ms14`` is omitted the source file is updated in place after a one-time ``*.placement-backup.ms14`` copy is saved next to it.

Report components whose bodies overlap in an .ms14 file (no COM call). Uses each component's pin-hull box plus ``clearance`` (the same geometry the wire router treats as an obstacle), so it tells you exactly where a dense custom layout would force wires through symbol bodies. Pure decode + geometry: runs in seconds and is the fast pre-check to run after ``set_component_positions`` or before rebuilding a board.

Dry-run a custom layout and report geometry findings in seconds. By default this runs the real builder (obstacle-aware routing included) into a scratch directory -- no Multisim launch, no files kept -- and returns the geometry preflight: final placements, component-overlap pairs, wire-through-body points and the resulting sheet size. With ``optimize=true, materialize=true`` and an explicit ``output_ms14``, the selected candidate is instead regenerated into a new file for the next native save/reopen and simulation gate.

Enlarge (or shrink) an .ms14 design's page and GUI working area. Sizes are inches at 96 dpi. Both page stores are kept in sync: the CircPrefs sheet dimensions that drive the image/export API and the DesignSheet WorkArea rectangle the GUI displays (a fixed A4 work area used to clip larger schematics on screen). Components are not moved. When ``output_ms14`` is omitted the source file is updated in place after a one-time ``*.sheet-backup.ms14`` copy is saved next to it.