Make

mohitmishra786/low-level-dev-skills/skills/build-systems/make

by mohitmishra786bdc58472fa9fNo license253 starsListed Oct 9, 2026Updated Oct 9, 2026Repository updated 3 months ago

GNU Make skill for C/C++ build systems. Use when writing or debugging Makefiles, understanding pattern rules and automatic dependency generation, managing CFLAGS/LDFLAGS, converting ad-hoc compile commands into maintainable Makefiles, or diagnosing incremental build issues. Activates on queries about Makefiles, make targets, pattern rules, phony targets, dependency tracking, recursive make, or make errors.

Instructions onlySoftware Development

AI-generated overview

Guides writing and debugging GNU Makefiles for C/C++ builds, covering pattern rules, dependency tracking and common errors.

What it does: Provides idiomatic GNU Makefile patterns for C and C++ projects, including minimal build files, pattern rules, automatic dependency generation with -MMD -MP, and debug/release configurations. It explains automatic variables, parallel and verbose builds, installation targets, and multi-directory project layouts. It also lists common make errors with causes and fixes, and points to a bundled cheatsheet for variable and function reference.
When to use it: Use when writing or debugging a Makefile for a C or C++ project, adding header dependency tracking, converting ad-hoc compile commands into a maintainable Makefile, or diagnosing incremental build problems and make errors.
Requirements: No scripts or tools are required beyond the agent; it is instructions only. It references a bundled cheatsheet file and assumes familiarity with GNU Make, a C/C++ compiler such as gcc, and a shell for running make commands.

GNU Make

Purpose

Guide agents through idiomatic Makefile patterns for C/C++ projects: phony targets, pattern rules, automatic dependency generation, and common build idioms.

Triggers

"How do I write a Makefile for my C project?"
"My Makefile rebuilds everything every time"
"How do I add dependency tracking to Make?"
"What does $@, $<, $^ mean?"
"I'm getting 'make: Nothing to be done for all'"
"How do I convert my shell compile script to a Makefile?"

Workflow

1. Minimal correct Makefile for C

makefile

CC      := gccCFLAGS  := -std=c11 -Wall -Wextra -g -O2LDFLAGS :=LDLIBS  :=
SRCS    := $(wildcard src/*.c)OBJS    := $(SRCS:src/%.c=build/%.o)TARGET  := build/prog
.PHONY: all clean
all: $(TARGET)
$(TARGET): $(OBJS)	$(CC) $(LDFLAGS) -o $@ $^ $(LDLIBS)
build/%.o: src/%.c | build	$(CC) $(CFLAGS) -c -o $@ $<
build:	mkdir -p build
clean:	rm -rf build

CC      := gccCFLAGS  := -std=c11 -Wall -Wextra -g -O2LDFLAGS :=LDLIBS  :=
SRCS    := $(wildcard src/*.c)OBJS    := $(SRCS:src/%.c=build/%.o)TARGET  := build/prog
.PHONY: all clean
all: $(TARGET)
$(TARGET): $(OBJS)	$(CC) $(LDFLAGS) -o $@ $^ $(LDLIBS)
build/%.o: src/%.c | build	$(CC) $(CFLAGS) -c -o $@ $<
build:	mkdir -p build
clean:	rm -rf build

Automatic variables:

$@ — target name
$< — first prerequisite
$^ — all prerequisites (deduplicated)
$* — stem (the % part in a pattern rule)
$(@D) — directory part of $@

2. Automatic dependency generation

Without this, changing a header doesn't trigger a rebuild of .c files that include it.

makefile

CC      := gccCFLAGS  := -std=c11 -Wall -Wextra -g -O2DEPFLAGS = -MMD -MP            # -MMD: generate .d file; -MP: phony targets for headers
SRCS    := $(wildcard src/*.c)OBJS    := $(SRCS:src/%.c=build/%.o)DEPS    := $(OBJS:.o=.d)TARGET  := build/prog
.PHONY: all clean
all: $(TARGET)
$(TARGET): $(OBJS)	$(CC) $(LDFLAGS) -o $@ $^ $(LDLIBS)
build/%.o: src/%.c | build	$(CC) $(CFLAGS) $(DEPFLAGS) -MF $(@:.o=.d) -c -o $@ $<
-include $(DEPS)    # '-' ignores errors on first build (no .d files yet)
build:	mkdir -p build
clean:	rm -rf build

CC      := gccCFLAGS  := -std=c11 -Wall -Wextra -g -O2DEPFLAGS = -MMD -MP            # -MMD: generate .d file; -MP: phony targets for headers
SRCS    := $(wildcard src/*.c)OBJS    := $(SRCS:src/%.c=build/%.o)DEPS    := $(OBJS:.o=.d)TARGET  := build/prog
.PHONY: all clean
all: $(TARGET)
$(TARGET): $(OBJS)	$(CC) $(LDFLAGS) -o $@ $^ $(LDLIBS)
build/%.o: src/%.c | build	$(CC) $(CFLAGS) $(DEPFLAGS) -MF $(@:.o=.d) -c -o $@ $<
-include $(DEPS)    # '-' ignores errors on first build (no .d files yet)
build:	mkdir -p build
clean:	rm -rf build

3. Pattern rules cheatsheet

makefile

# Compile C%.o: %.c	$(CC) $(CFLAGS) -c -o $@ $<
# Compile C++%.o: %.cpp	$(CXX) $(CXXFLAGS) -c -o $@ $<
# Generate assembly%.s: %.c	$(CC) $(CFLAGS) -S -o $@ $<
# Run a tool on each filebuild/%.processed: src/%.raw | build	mytool $< > $@

# Compile C%.o: %.c	$(CC) $(CFLAGS) -c -o $@ $<
# Compile C++%.o: %.cpp	$(CXX) $(CXXFLAGS) -c -o $@ $<
# Generate assembly%.s: %.c	$(CC) $(CFLAGS) -S -o $@ $<
# Run a tool on each filebuild/%.processed: src/%.raw | build	mytool $< > $@

4. Common Make patterns

Debug and release builds

makefile

BUILD ?= release
ifeq ($(BUILD),debug)  CFLAGS += -g -Og -DDEBUGelse  CFLAGS += -O2 -DNDEBUGendif

BUILD ?= release
ifeq ($(BUILD),debug)  CFLAGS += -g -Og -DDEBUGelse  CFLAGS += -O2 -DNDEBUGendif

Usage: make BUILD=debug

Parallel builds

Add -Otarget (or -O) for ordered output: make -j$(nproc) -O

Verbose output

makefile

# In Makefile: suppress with @build/%.o: src/%.c | build	@echo "  CC  $<"	@$(CC) $(CFLAGS) -c -o $@ $<

# In Makefile: suppress with @build/%.o: src/%.c | build	@echo "  CC  $<"	@$(CC) $(CFLAGS) -c -o $@ $<

Override silence: make V=1 if you guard with $(V):

Installing

makefile

PREFIX ?= /usr/local
install: $(TARGET)	install -d $(DESTDIR)$(PREFIX)/bin	install -m 0755 $(TARGET) $(DESTDIR)$(PREFIX)/bin/

PREFIX ?= /usr/local
install: $(TARGET)	install -d $(DESTDIR)$(PREFIX)/bin	install -m 0755 $(TARGET) $(DESTDIR)$(PREFIX)/bin/

5. Multi-directory projects

For medium projects, avoid recursive make (fragile, slow). Use a flat Makefile that includes sub-makefiles:

makefile

# lib/module.mkLIB_SRCS := $(wildcard lib/*.c)LIB_OBJS := $(LIB_SRCS:lib/%.c=build/lib_%.o)OBJS      += $(LIB_OBJS)
build/lib_%.o: lib/%.c	$(CC) $(CFLAGS) -c -o $@ $<

# lib/module.mkLIB_SRCS := $(wildcard lib/*.c)LIB_OBJS := $(LIB_SRCS:lib/%.c=build/lib_%.o)OBJS      += $(LIB_OBJS)
build/lib_%.o: lib/%.c	$(CC) $(CFLAGS) -c -o $@ $<

6. Common errors

Error	Cause	Fix
`No rule to make target 'foo.o'`	Missing source or rule	Check source path and pattern rule
`Nothing to be done for 'all'`	Targets up to date	Touch a source file or run `make clean`
`Circular dependency dropped`	Target depends on itself	Check dependency chain
`missing separator`	Tab vs spaces	Recipes must use a tab, not spaces
`*** multiple target patterns`	Pattern rule syntax error	Check `%` placement
Rebuilds everything every time	Timestamps wrong, or PHONY missing	Check `date`; ensure `all` is `.PHONY`
Header change not detected	No dep tracking	Add `-MMD -MP` and `-include $(DEPS)`

For a full variable and function reference, see references/cheatsheet.md [blocked].

Related skills

Use skills/build-systems/cmake for CMake-based projects
Use skills/build-systems/ninja for Ninja as a make backend
Use skills/compilers/gcc for CFLAGS details

Source and attribution

Source:mohitmishra786/low-level-dev-skillsinskills/build-systems/makeat commitbdc5847

License: No license

Content belongs to its original authors. SourceWeft indexes it from a public repository.

Report or request removal

Make

GNU Make

Purpose

Triggers

Workflow

1. Minimal correct Makefile for C

2. Automatic dependency generation

3. Pattern rules cheatsheet

4. Common Make patterns

Debug and release builds

Parallel builds

Verbose output

Installing

5. Multi-directory projects

6. Common errors

Related skills

Source and attribution

More from mohitmishra786/low-level-dev-skills

Zig Debugging

Simd Intrinsics

Zig Cross

Rustc Basics

Zig Cinterop

Zig Build System

More in Software Development

Playground

M5 Onboard

Cardputer Buddy

Web Design Guidelines

Vercel React Native Skills

Vercel React Best Practices