Assembly Arm

ARM / AArch64 Assembly

Purpose

Guide agents through AArch64 (64-bit) and ARM (32-bit Thumb) assembly: registers, calling conventions, inline asm, and NEON/SVE SIMD patterns.

Triggers

• "How do I read ARM64 assembly output?"
• "What are the AArch64 registers and calling convention?"
• "How do I write inline asm for ARM?"
• "What is the difference between AArch64 and ARM Thumb?"
• "How do I use NEON intrinsics?"

Workflow

1. Generate ARM assembly

# AArch64 (native or cross-compile)aarch64-linux-gnu-gcc -S -O2 foo.c -o foo.s
# 32-bit ARM Thumbarm-linux-gnueabihf-gcc -S -O2 -mthumb foo.c -o foo.s
# From objdumpaarch64-linux-gnu-objdump -d -S prog
# From GDB on target(gdb) disassemble /s main

2. AArch64 registers (AAPCS64)

Width variants: x0 (64-bit), w0 (32-bit, zero-extends to 64), h0 (16), b0 (8).

3. AAPCS64 calling convention

Integer/pointer args: x0–x7 Float/SIMD args: v0–v7 Return: x0 (int), x0+x1 (128-bit), v0 (float/SIMD) Callee-saved: x19–x28, x29 (fp), x30 (lr), v8–v15 (lower 64 bits) Caller-saved: everything else

Stack must be 16-byte aligned at any bl or blr instruction.

4. Common AArch64 instructions

5. Typical function prologue/epilogue

// Non-leaf functionstp  x29, x30, [sp, #-32]!   // save fp, lr; allocate 32 bytesmov  x29, sp                  // set frame pointerstp  x19, x20, [sp, #16]     // save callee-saved registers// ... body ...ldp  x19, x20, [sp, #16]     // restoreldp  x29, x30, [sp], #32     // restore fp, lr; deallocateret
// Leaf function (no calls, no callee-saved regs needed)// Can use red zone (no rsp adjustment) — but AArch64 has no red zonesub  sp, sp, #16             // allocate locals// ... body ...add  sp, sp, #16ret

6. Inline assembly (GCC/Clang)

// Barrier__asm__ volatile ("dmb ish" ::: "memory");
// Load acquirestatic inline int load_acquire(volatile int *p) {    int val;    __asm__ volatile ("ldar %w0, %1" : "=r"(val) : "Q"(*p));    return val;}
// Store releasestatic inline void store_release(volatile int *p, int val) {    __asm__ volatile ("stlr %w1, %0" : "=Q"(*p) : "r"(val));}
// Read system counterstatic inline uint64_t read_cntvct(void) {    uint64_t val;    __asm__ volatile ("mrs %0, cntvct_el0" : "=r"(val));    return val;}

AArch64-specific constraints:

• "Q" — memory operand suitable for exclusive/acquire/release instructions
• "r" — any general-purpose register
• "w" — any FP/SIMD register

7. NEON SIMD intrinsics

#include <arm_neon.h>
// Add 4 floats at oncefloat32x4_t a = vld1q_f32(arr_a);   // load 4 floatsfloat32x4_t b = vld1q_f32(arr_b);float32x4_t c = vaddq_f32(a, b);vst1q_f32(result, c);
// Horizontal sumfloat32x4_t sum = vpaddq_f32(c, c);sum = vpaddq_f32(sum, sum);float total = vgetq_lane_f32(sum, 0);

Naming convention: v<op><q>_<type>

• q suffix: 128-bit (quad) vector
• _f32: float32, _s32: int32, _u8: uint8, etc.

8. Darwin vs Linux AArch64 ABI differences

On macOS/iOS, avoid using x18; use _DARWIN_C_LEVEL headers for platform types.

9. AMX primer (Apple Silicon)

Apple Matrix coprocessor (AMX) is not exposed via public intrinsics. Access paths:

// Practical: Accelerate/vecLib uses AMX internally#include <Accelerate/Accelerate.h>// cblas_sgemm, vDSP_* dispatch to AMX on M-series
// Low-level: community-documented opcodes — not portable, avoid in production

Prefer Metal Performance Shaders or Accelerate for matrix workloads on Apple Silicon (skills/platform/apple-silicon).

10. 16KB page size on Apple M-series

macOS on Apple Silicon uses 16KB pages (not 4KB):

#include <unistd.h>long page = sysconf(_SC_PAGESIZE);  // 16384 on macOS arm64// Align mmap and posix_memalign to page size

Code assuming PAGE_SIZE == 4096 may misalign buffers or fail mmap on macOS.

11. NEON → SVE2 migration hints

Porting checklist├── Replace 128-bit fixed loops with svcnt*() strides on SVE hardware├── Use predicates (svwhilelt) for tails instead of scalar epilogues├── Guard SVE code with #ifdef __ARM_FEATURE_SVE└── Keep NEON path for Apple M1–M3 (no SVE); use SVE2 on Graviton/M4+

See skills/platform/arm-sve for SVE intrinsics and auto-vectorization flags.

For a register reference, see references/reference.md [blocked].

Related skills

• Use skills/low-level-programming/assembly-x86 for x86-64 assembly
• Use skills/compilers/cross-gcc for cross-compilation toolchain
• Use skills/debuggers/gdb for debugging ARM code with gdbserver
• Use skills/platform/arm-sve for SVE/SVE2 scalable vectors
• Use skills/platform/apple-silicon for M-series unified memory and AMX