Assembly X86

x86-64 Assembly

Purpose

Guide agents through x86-64 assembly: reading compiler output, understanding the ABI, writing inline asm, and common patterns.

Triggers

• "How do I read the assembly GCC generated?"
• "What are the x86-64 registers?"
• "What is the calling convention on Linux/macOS?"
• "How do I write inline assembly in C?"
• "How do I use SSE/AVX intrinsics?"
• "This assembly uses %rsp / %rbp — what does it mean?"

Workflow

1. Generate and read assembly

# AT&T syntax (GCC default)gcc -S -O2 -fverbose-asm foo.c -o foo.s
# Intel syntaxgcc -S -masm=intel -O2 foo.c -o foo.s
# From GDB(gdb) disassemble /s main    # with source(gdb) x/20i $rip
# From objdumpobjdump -d -M intel -S prog  # Intel + source (needs -g)

2. x86-64 registers

3. System V AMD64 ABI (Linux, macOS, FreeBSD)

Integer/pointer argument registers (in order): %rdi, %rsi, %rdx, %rcx, %r8, %r9

Floating-point argument registers: %xmm0–%xmm7

Return values:

• Integer: %rax (low), %rdx (high if 128-bit)
• Float: %xmm0 (low), %xmm1 (high)

Caller-saved (scratch): %rax, %rcx, %rdx, %rsi, %rdi, %r8–%r11, %xmm0–%xmm15

Callee-saved (must preserve): %rbx, %rbp, %r12–%r15

Stack: 16-byte aligned before call; call pushes 8 bytes → 16-byte aligned at function entry after prologue.

Red zone: 128 bytes below %rsp may be used by leaf functions without adjusting %rsp. Not available in kernel/signal handlers.

4. Common instruction patterns

5. AT&T vs Intel syntax

GCC emits AT&T by default. Use -masm=intel for Intel syntax.

6. Inline assembly (GCC extended asm)

// Basic: increment a registerint x = 5;__asm__ volatile (    "incl %0"    : "=r"(x)   // outputs: =r means write-only register    : "0"(x)    // inputs: 0 means same as output 0    : // clobbers: none);
// CPUID exampleuint32_t eax, ebx, ecx, edx;__asm__ volatile (    "cpuid"    : "=a"(eax), "=b"(ebx), "=c"(ecx), "=d"(edx)    : "a"(1)    // input: leaf 1);
// Atomic incrementstatic inline int atomic_inc(volatile int *p) {    int ret;    __asm__ volatile (        "lock; xaddl %0, %1"        : "=r"(ret), "+m"(*p)        : "0"(1)        : "memory"    );    return ret + 1;}

Constraint codes:

• "r" — any general register
• "m" — memory operand
• "i" — immediate integer
• "a", "b", "c", "d" — specific registers (%rax, %rbx, %rcx, %rdx)
• "=" prefix — output (write-only)
• "+" prefix — read-write
• "memory" clobber — tells compiler memory may be modified (barrier)

7. SSE/AVX intrinsics (preferred over inline asm)

#include <immintrin.h>   // includes all x86 SIMD headers
// Add 8 floats at once with AVX__m256 a = _mm256_loadu_ps(arr_a);   // load 8 floats (unaligned)__m256 b = _mm256_loadu_ps(arr_b);__m256 c = _mm256_add_ps(a, b);_mm256_storeu_ps(result, c);

Check CPU support at compile time: -mavx2 or -march=native. Check at runtime: __builtin_cpu_supports("avx2").

For a full register and instruction reference, see references/reference.md [blocked].

Related skills

• Use skills/low-level-programming/assembly-arm for AArch64/ARM assembly
• Use skills/compilers/gcc for -S -masm=intel flag details
• Use skills/debuggers/gdb for stepping through assembly (si, ni, x/i)